Datasheet

Section 7 DMA Controller (DMAC)
R01UH0310EJ0500 Rev. 5.00 Page 317 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
7.2 Input/Output Pins
Table 7.1 shows the pin configuration of the interrupt controller.
Table 7.1 Pin Configuration
Channel Pin Name Symbol I/O Function
0 DMA request 0 DREQ0 Input Channel 0 external request
DMA transfer acknowledge 0 DACK0 Output Channel 0 single address
transfer acknowledge
DMA transfer end 0 TEND0 Output Channel 0 transfer end
1 DMA request 1 DREQ1 Input Channel 1 external request
DMA transfer acknowledge 1 DACK1 Output Channel 1 single address
transfer acknowledge
DMA transfer end 1 TEND1 Output Channel 1 transfer end