Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 311 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(4) EXDMAC
The EXDMAC sends the bus arbiter a request for the bus when an activation request is generated.
As the EXDMAC is used exclusively for transfers to and from the external bus, if the bus is
transferred to the EXDMAC, internal accesses by other internal bus masters are still executed in
parallel.
In normal transfer mode or cycle steal transfer mode, the EXDMAC releases the bus after a single
transfer.
In block transfer mode, it releases the bus after transfer of one block, and in burst transfer mode,
after completion of the transfer. By setting the BGUP bit to 1 in EDMDR, it is possible to specify
temporary release of the bus in the event of an external access request from an internal bus master.
For details see section 8, EXDMA Controller (EXDMAC).
Note: The EXDMAC is not supported by the H8S/2424 Group.
(5) External Bus Release
When the BREQ pin goes low and an external bus release request is issued while the BRLE bit is
set to 1 in BCR, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
6.14 Bus Controller Operation in Reset
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.