Datasheet

Section 6 Bus Controller (BSC)
Page 306 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
If an external bus release request and external access occur simultaneously, the order of priority is
as follows:
(High) External bus release > External access by internal bus master (Low)
If a refresh request*
2
and external bus release request occur simultaneously, the order of priority is
as follows:
(High) Refresh*
2
> External bus release (Low)
Notes: 1. Not supported by the H8S/2424 Group.
2. Not supported by the 5-V version.
6.12.2 Pin States in External Bus Released State
Table 6.14 shows pin states in the external bus released state.
Table 6.14 Pin States in Bus Released State
Pins Pin State
A23 to A0 High impedance
D15 to D0 High impedance
CSn (n = 7 to 0) High impedance
UCAS, LCAS High impedance
AS/AH High impedance
RD High impedance
OE High impedance
HWR, LWR High impedance
DACKn (n = 1, 0) High
EDACKn* (n = 3, 2) High
Note: * Not supported by the H8S/2424 Group.