Datasheet
Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 305 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.12 Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters except the EXDMAC*
1
continue to operate as
long as there is no external access. If any of the following requests are issued in the external bus
released state, the BREQO signal can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request*
2
is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode
Notes: *1 Not supported by the H8S/2424 Group.
*2 The refresh control is not supported by the 5-V version.
6.12.1 Operation
In externally expanded mode, the bus can be released to an external device by setting the BRLE
bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus released state.
In the external bus released state, internal bus masters except the EXDMAC*
1
can perform
accesses using the internal bus. When an internal bus master wants to make an external access, it
temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus
master to be canceled. If a refresh request is generated in the external bus released state, or if a
SLEEP instruction is executed to place the chip in software standby mode or all-module-clocks-
stopped mode, refresh control and software standby or all-module-clocks-stopped control is
deferred until the bus request from the external bus master is canceled.
If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the
following requests are issued, to request cancellation of the bus request externally.
• When an internal bus master wants to perform an external access
• When a refresh request*
2
is generated
• When a SLEEP instruction is executed to place the chip in software standby mode or all-
module-clocks-stopped mode