Datasheet

Section 6 Bus Controller (BSC)
Page 298 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(b) Normal space access after a continuous synchronous DRAM space write access
If a normal space read cycle occurs after a continuous synchronous DRAM space write access
while the ICIS2 bit is set to 1 in BCR, idle cycle is inserted at the start of the read cycle. The
number of states of the idle cycle to be inserted is in accordance with the setting of bit IDLC. It is
not in accordance with the DRMI bit in DRACCR.
Figure 6.92 shows an example of idle cycle operation when the ICIS2 bit is set to 1.
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
c2
T
3
T
c1
Continuous synchronous
DRAM space write External address space read
Synchronous
DRAM space read
T
2
T
i
T
1
RAS
CAS
WE
RD
HWR, LWR
CKE
High
PALL ACTV NOP WRIT
NOP NOPREAD
DQMU, DQML
T
Cl
T
c2
Precharge-sel
φ
External address
External address
Column
address
Column address 2
Row
address
Row
address
Column
address
Figure 6.92 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Write Access (IDLC = 0, ICIS1 = 0, SDWCD = 1, CAS Latency 2)