Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 297 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(a) Normal space access after a continuous synchronous DRAM space read access
While the DRMI bit is cleared to 0 in DRACCR, idle cycle insertion after continuous synchronous
DRAM space read access is disabled. Idle cycle insertion after continuous synchronous DRAM
space read access can be enabled by setting the DRMI bit to 1. The conditions and number of
states of the idle cycle to be inserted are in accordance with the settings of bits ICIS1, ICIS0, and
IDLC in RCR. Figure 6.91 shows an example of idle cycle operation when the DRMI bit is set to
1. When the DRMI bit is cleared to 0, an idle cycle is not inserted after continuous synchronous
DRAM space read access even if bits ICIS1 and ICIS0 are set to 1.
T
p
Address bus
Idle cycle
Data bus
T
r
T
c1
T
cl
T
c2
T
3
T
i
T
c1
Continuous synchronous
DRAM space read External space read
Continuous synchronous
DRAM space read
T
2
T
i
T
1
RAS
CAS
WE
RD
CKE
High
PALL ACTV READ
NOP NOPREAD
DQMU, DQML
T
Cl
T
c2
Precharge-sel
φ
External address
External address
Column address 1 Column address 2
Row
address
Row
address
Column
address
Figure 6.91 Example of Idle Cycle Operation after Continuous Synchronous DRAM Space
Read Access (Read between Different Area) (IDLC = 0, CAS Latency 2)