Datasheet

Section 6 Bus Controller (BSC)
Page 278 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
When DDS = 0 or EDDS = 0: When continuous synchronous DRAM space is accessed in
DMAC or EXDMAC single address transfer mode, full access (normal access) is always
performed. With the synchronous DRAM interface, the DACK or EDACK output goes low from
the T
r
state.
In modes other than DMAC or EXDMAC single address transfer mode, burst access can be used
when accessing continuous synchronous DRAM space.
Figure 6.73 shows the DACK or EDACK output timing for connecting the synchronous DRAM
interface when DDS = 0 or EDDS = 0.