Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 275 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.8.14 Mode Register Setting of Synchronous DRAM
To use synchronous DRAM, mode must be set after power-on. To set mode, set the RMTS2 to
RMTS0 bits in DRAMCR to H'5 and enable the synchronous DRAM mode register setting. After
that, access the continuous synchronous DRAM space in bytes. When the value to be set in the
synchronous DRAM mode register is X, value X is set in the synchronous DRAM mode register
by writing to the continuous synchronous DRAM space of address H'400000 + X for 8-bit bus
configuration synchronous DRAM and by writing to the continuous synchronous DRAM space of
address H'400000 + 2X for 16-bit bus configuration synchronous DRAM.
The value of the address signal is fetched at the issuance time of the MRS command as the setting
value of the mode register in the synchronous DRAM. Mode of burst read/burst write in the
synchronous DRAM is not supported by this LSI. For setting the mode register of the synchronous
DRAM, set the burst read/single write with the burst length of 1. Figure 6.71 shows the setting
timing of the mode in the synchronous DRAM.
T
p
φ
SDRAMφ
RAS
CAS
WE
CKE
PALL MRS NOPNOP
Address bus
T
r
T
c1
T
c2
Mode setting value
Mode setting value
Precharge-sel
High
Figure 6.71 Synchronous DRAM Mode Setting Timing