Datasheet

Section 6 Bus Controller (BSC)
Page 260 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
The setting of bits TPC1 and TPC0 is also valid for T
p
states in refresh cycles.
T
p1
SDRAMφ
RAS
Read
CAS
WE
CKE
PALL NOP ACTV READ NOP
DQMU, DQML
Data bus
Address bus
T
p2
T
r
T
c1
T
cl
T
c2
Row addressColumn address Column address
Precharge-sel
Row address
High
RAS
Write
CAS
WE
CKE
PALL NOP NOPACTV NOPWRIT
DQMU, DQML
Data bus
High
φ
Figure 6.59 Example of Timing with Two-State Precharge Cycle
(TPC1 = 0, TPC0 = 1, SDWCD = 0, CAS Latency 2)