Datasheet

Section 6 Bus Controller (BSC)
Page 250 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.8 Synchronous DRAM Interface
In the H8S/2426R Group, external address space areas 2 to 5 can be designated as continuous
synchronous DRAM space, and synchronous DRAM interfacing performed. The synchronous
DRAM interface allows synchronous DRAM to be directly connected to this LSI. A synchronous
DRAM space of up to 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
Synchronous DRAM of CAS latency 1 to 4 can be connected.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Group.
6.8.1 Setting Continuous Synchronous DRAM Space
Areas 2 to 5 are designated as continuous synchronous DRAM space by setting bits RMTS2 to
RMTS0 in DRAMCR. The relation between the settings of bits RMTS2 to RMTS0 and
synchronous DRAM space is shown in table 6.8. Possible synchronous DRAM interface settings
are and continuous area (areas 2 to 5).
Table 6.8 Relation between Settings of Bits RMTS2 to RMTS0 and Synchronous DRAM
Space
RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2
0 1 Normal space Normal space Normal space DRAM space
0 Normal space Normal space DRAM space DRAM space
0
1
1 DRAM space DRAM space DRAM space DRAM space
0 Continuous synchronous DRAM space 0
1 Mode settings of synchronous DRAM
0 Reserved (setting prohibited)
1
1
1 Continuous DRAM space
With continuous synchronous DRAM space, CS2, CS3, CS4 pins are used as RAS, CAS, WE
signal. The OE pin of the DRAM is used as the CKE signal, and the CS5 pin is used as
synchronous DRAM clock (SDRAMφ). The bus specifications for continuous synchronous
DRAM space conform to the settings for area 2. The pin wait and program wait for the continuous
synchronous DRAM are invalid.
Commands for the synchronous DRAM can be specified by combining RAS, CAS, WE, and
address-precharge-setting command (Precharge-sel) output on the upper column addresses.