Datasheet

Section 6 Bus Controller (BSC)
Page 244 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Depending on the DRAM used, modification of the WE signal may not be permitted during the
refresh period. In this case, the CBRM bit in REFCR should be set to 1. The bus controller will
then insert refresh cycles in appropriate breaks between bus cycles. Figure 6.50 shows an example
of the timing when the CBRM bit is set to 1. In this case the CS signal is not controlled, and
retains its value prior to the start of the refresh period.
A
23 to A0
φ
CS
AS
RD
HWR (WE)
CAS
Normal space access request
RAS
Refresh period
Figure 6.50 Example of CBR Refresh Timing (CBRM = 1)