Datasheet

Page xxvii of xxx
21.8 Boot Mode ....................................................................................................................... 1099
21.9 SCI Boot Mode ................................................................................................................ 1099
21.10 Serial Communication Interface Specification for Boot Mode........................................ 1100
21.11 Programmer Mode ........................................................................................................... 1130
Section 22 Clock Pulse Generator ...................................................................1131
22.1 Register Descriptions....................................................................................................... 1132
22.1.1 System Clock Control Register (SCKCR) .......................................................... 1132
22.1.2 PLL Control Register (PLLCR).......................................................................... 1134
22.2 Oscillator.......................................................................................................................... 1135
22.2.1 Connecting a Crystal Resonator.......................................................................... 1135
22.2.2 External Clock Input........................................................................................... 1136
22.3 System-Clock PLL Circuit and Divider........................................................................... 1138
22.4 Usage Notes ..................................................................................................................... 1139
22.4.1 Notes on Clock Pulse Generator......................................................................... 1139
22.4.2 Notes on Resonator............................................................................................. 1139
22.4.3 Notes on Board Design ....................................................................................... 1140
Section 23 Power-Down Modes ......................................................................1141
23.1 Register Descriptions....................................................................................................... 1145
23.1.1 Standby Control Register (SBYCR) ................................................................... 1145
23.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) .................. 1147
23.1.3 Extension Module Stop Control Registers H and L
(EXMSTPCRH, EXMSTPCRL) ........................................................................ 1148
23.1.4 RAM Module Stop Control Registers H and L
(RMMSTPCRH, RMMSTPCRL)....................................................................... 1149
23.2 Operation ......................................................................................................................... 1151
23.2.1 Clock Division Mode.......................................................................................... 1151
23.2.2 Sleep Mode ......................................................................................................... 1152
23.2.3 Software Standby Mode...................................................................................... 1153
23.2.4 Hardware Standby Mode .................................................................................... 1156
23.2.5 Module Stop Function ........................................................................................ 1157
23.2.6 All Module Clocks Stop Mode ........................................................................... 1158
23.3 φ Clock Output Control.................................................................................................... 1159
23.4 SDRAMφ Clock Output Control ..................................................................................... 1160
23.5 Usage Notes ..................................................................................................................... 1161
23.5.1 I/O Port Status..................................................................................................... 1161
23.5.2 Current Dissipation during Oscillation Stabilization Standby Period................. 1161
23.5.3 EXDMAC, DMAC, and DTC Module Stop....................................................... 1161
23.5.4 On-Chip Peripheral Module Interrupts ............................................................... 1161