Datasheet

Section 6 Bus Controller (BSC)
Page 236 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.7.11 Burst Operation
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making
consecutive accesses to the same row address. This mode enables fast (burst) access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
(1) Burst Access (Fast Page Mode)
Figures 6.42 and 6.43 show the operation timing for burst access. When there are consecutive
access cycles for DRAM space, the CAS signal and column address output cycles (two states)
continue as long as the row address is the same for consecutive access cycles. The row address
used for the comparison is set with bits MXC2 to MXC0 in DRAMCR.