Datasheet

Section 6 Bus Controller (BSC)
Page 234 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.7.10 Byte Access Control
When DRAM with a ×16-bit configuration is connected, the 2-CAS access method is used for the
control signals needed for byte access. Figure 6.40 shows the control timing for 2-CAS access,
and figure 6.41 shows an example of 2-CAS DRAM connection.
T
p
RASn (CSn)
UCAS
LCAS
WE (HWR)
OE (RD)
Upper data bus
Lower data bus
Address bus
φ
T
r
T
c1
T
c2
Note: n = 2 to 5
Row address Column address
Write data
High
High
High-Z
Figure 6.40 2-CAS Control Timing
(Upper Byte Write Access: RAST = 0, CAST = 0)