Datasheet

Section 6 Bus Controller (BSC)
Page 190 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(3) Areas 2 to 5
In externally expanded mode, areas 2 to 5 are all external address space.
When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.
The basic bus interface, DRAM interface, or synchronous DRAM interface can be selected for the
memory interface of areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS2
to RAS5 signals.
If areas 2 to 5 are designated as continuous DRAM space, large-capacity (e.g. 64-Mbit) DRAM
can be connected. In this case, the CS2 signal is used as the RAS signal for the continuous DRAM
space.
If areas 2 to 5 are designated as continuous synchronous DRAM space, large-capacity (e.g. 64-
Mbit) synchronous DRAM can be connected. In this case, the CS2, CS3, CS4, and CS5 pins are
used as the RAS, CAS, WE, and CLK signals for the continuous synchronous DRAM space. The
OE pin is used as the CKE signal.
(4) Area 6
In externally expanded mode, all of area 6 is external space.
When area 6 external space is accessed, the CS6 signal can be output.
Either the basic bus interface or address/data multiplexed I/O interface can be used for the
memory interface of area 6.
(5) Area 7
Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode, the space
excluding the on-chip RAM and internal I/O registers is external address space. The on-chip RAM
is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when the
RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external address space.
When area 7 external address space is accessed, the CS7 signal can be output.
Either the basic bus interface or address/data multiplexed I/O interface can be used for the
memory interface of area 7.