Datasheet

Page xxi of xxx
12.4.6 Example of Non-Overlapping Pulse Output
(Example of Four-Phase Complementary Non-Overlapping Output) .................. 822
12.4.7 Inverted Pulse Output ........................................................................................... 824
12.4.8 Pulse Output Triggered by Input Capture............................................................. 825
12.5 Usage Notes ....................................................................................................................... 826
12.5.1 Module Stop Function Setting .............................................................................. 826
12.5.2 Operation of Pulse Output Pins............................................................................. 826
Section 13 8-Bit Timers (TMR).........................................................................827
13.1 Features.............................................................................................................................. 827
13.2 Input/Output Pins...............................................................................................................829
13.3 Register Descriptions......................................................................................................... 829
13.3.1 Timer Counter (TCNT)......................................................................................... 830
13.3.2 Time Constant Register A (TCORA).................................................................... 830
13.3.3 Time Constant Register B (TCORB).................................................................... 830
13.3.4 Timer Control Register (TCR).............................................................................. 831
13.3.5 Timer Counter Control Register (TCCR) ............................................................. 832
13.3.6 Timer Control/Status Register (TCSR)................................................................. 834
13.4 Operation ........................................................................................................................... 838
13.4.1 Pulse Output.......................................................................................................... 838
13.4.2 Reset Input ............................................................................................................ 839
13.5 Operation Timing............................................................................................................... 840
13.5.1 TCNT Incrementation Timing .............................................................................. 840
13.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................. 841
13.5.3 Timing of Timer Output when Compare-Match Occurs....................................... 842
13.5.4 Timing of Compare Match Clear.......................................................................... 842
13.5.5 Timing of TCNT External Reset........................................................................... 843
13.5.6 Timing of Overflow Flag (OVF) Setting .............................................................. 843
13.6 Operation with Cascaded Connection................................................................................ 844
13.6.1 16-Bit Counter Mode ............................................................................................ 844
13.6.2 Compare Match Count Mode................................................................................ 844
13.7 Interrupt Sources................................................................................................................ 845
13.7.1 Interrupt Sources and DTC Activation ................................................................. 845
13.7.2 A/D Converter Activation..................................................................................... 845
13.8 Usage Notes ....................................................................................................................... 846
13.8.1 Contention between TCNT Write and Clear......................................................... 846
13.8.2 Contention between TCNT Write and Increment ................................................. 847
13.8.3 Contention between TCOR Write and Compare Match ....................................... 848
13.8.4 Contention between Compare Matches A and B .................................................. 849
13.8.5 Switching of Internal Clocks and TCNT Operation ............................................. 849