Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 179 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.3.10 DRAM Access Control Register (DRACCR)
DRACCR is used to set the DRAM/synchronous DRAM interface bus specifications.
Note: The synchronous DRAM interface is not supported by the H8S/2426 Group and H8S/2424
Group. The DRAM interface is not supported by the 5-V version.
Bit Bit Name Initial Value R/W Description
15 DRMI 0 R/W Idle Cycle Insertion
An idle cycle can be inserted after a
DRAM/synchronous DRAM access cycle when a
continuous normal space access cycle follows a
DRAM/synchronous DRAM access cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS2,
ICIS1, ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
14 ⎯ 0 R/W Reserved
This bit can be read from or written to. However,
the write value should always be 0.
13
12
TPC1
TPC0
0
0
R/W
R/W
Precharge State Control
These bits select the number of states in the RAS
precharge cycle in normal access and refreshing.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
11 SDWCD 0* R/W CAS Latency Control Cycle Disabled during
Continuous Synchronous DRAM Space Write
Access
Disables CAS latency control cycle (Tcl) inserted
by WTCRB (H) settings during synchronous
DRAM write access (see figure 6.5).
0: Enables CAS latency control cycle
1: Disables CAS latency control cycle