Datasheet

Section 6 Bus Controller (BSC)
Page 178 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name Initial Value R/W Description
2
1
0
MXC2
MXC1
MXC0
0
0
0
R/W
R/W
R/W
111: 11-bit shift
• When 8-bit access space is designated:
Row address bits A23 to A11 used for
comparison
• When 16-bit access space is designated:
Row address bits A23 to A12 used for
comparison
The precharge-sel is A15 to A12 of the column
address.
T
p
A
ddress
φ
RAST = 0 RAS
RAST = 1 RAS
T
r
T
c1
T
c2
UCAS, LCAS
Bus cycle
Row address Column address
Figure 6.4 RAS Signal Assertion Timing
(2-State Column Address Output Cycle, Full Access)