Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 163 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.3.4 Read Strobe Timing Control Register (RDNCR)
RDNCR selects the read strobe signal (RD) negation timing in a basic bus interface read access.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Strobe Timing Control 7 to 0
These bits set the negation timing of the read
strobe in a corresponding area read access.
As shown in figure 6.2, the read strobe for an area
for which the RDNn bit is set to 1 is negated one
half-state earlier than that for an area for which the
RDNn bit is cleared to 0. The read data setup and
hold time specifications are also one half-state
earlier.
0: In an area n read access, the RD is negated at
the end of the read cycle
1: In an area n read access, the RD is negated
one half-state before the end of the read cycle
(n = 7 to 0)