Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 157 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
6.3.3 Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH,
and WTCRBL)
WTCRA and WTCRB select the number of program wait states for each area in the external
address space.
In addition, CAS latency is set when a synchronous DRAM* is connected.
Note: * The synchronous DRAM interface is not supported by the H8S/2426 Group and
H8S/2424 Group.
• WTCRAH
Bit Bit Name Initial Value R/W Description
15 ⎯ 0 R Reserved
This bit is always read as 0 and cannot be
modified.
14
13
12
W72
W71
W70
1
1
1
R/W
R/W
R/W
Area 7 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 7 while AST7 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
11 ⎯ 0 R Reserved
This bit is always read as 0 and cannot be
modified.