Datasheet

Section 6 Bus Controller (BSC)
Page 150 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
• Idle cycle insertion
Idle cycles can be inserted between external read cycles to different areas
Idle cycles can be inserted before the write cycle after a read cycle
Idle cycles can be inserted before the read cycle after a write cycle
• Write buffer function
External write cycles and internal accesses can be executed in parallel
DMAC single address transfers and internal accesses can be executed in parallel
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU, DMAC, DTC, and
EXDMAC*
3
Notes: 1. Not supported by the 5-V version.
2. Not supported by the H8S/2426 Group and H8S/2424 Group.
3. Not supported by the H8S/2424 Group.