Datasheet

Section 6 Bus Controller (BSC)
R01UH0310EJ0500 Rev. 5.00 Page 149 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
mastership⎯the CPU, DMA controller (DMAC), EXDMA controller (EXDMAC)*, and data
transfer controller (DTC). A block diagram of the bus controller is shown in figure 6.1.
Note: * Not supported by the H8S/2424 Group.
6.1 Features
• Manages external address space in area units
Manages the external address space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
Burst ROM, DRAM*
1
, synchronous DRAM*
2
, and address/data multiplexed I/O interfaces can
be set
• Basic bus interface
Chip select signals (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait cycles can be inserted for each area
Extension cycles can be inserted while CS is asserted for each area
Wait cycles can be inserted by the WAIT pin
The negation timing of the read strobe signal (RD) can be modified
• Burst ROM interface
Burst ROM interface can be set independently for areas 0 and 1
• Address/data multiplexed I/O interface
Address/data multiplexed I/O interface can be set for areas 6 and 7
• DRAM interface*
1
DRAM interface can be set for areas 2 to 5
• Synchronous DRAM interface*
2
Continuous synchronous DRAM space can be set for areas 2 to 5