Datasheet

Section 5 Interrupt Controller
R01UH0310EJ0500 Rev. 5.00 Page 145 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
5.7 Usage Notes
5.7.1 Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction
such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the
interrupt concerned will still be enabled on completion of the instruction, and so interrupt
exception handling for that interrupt will be executed on completion of the instruction. However,
if there is an interrupt request of higher priority than that interrupt, interrupt exception handling
will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0. Figure 5.6 shows an example
in which the TCIEV bit in the TPU's TIER_0 register is cleared to 0. The above conflict will not
occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
Internal
address bus
Internal
write signal
φ
TCIEV
TCFV
TCIV
interrupt signal
TIER_0 write cycle by CPU
TCIV exception handling
TIER_0 address
Figure 5.6 Conflict between Interrupt Generation and Disabling