Datasheet

Section 5 Interrupt Controller
Page 144 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Table 5.5 Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8 Bit Bus 16 Bit Bus
Symbol
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch S
I
1 4 6+2m 2 3+m
Branch address read S
J
Stack manipulation S
K
[Legend]
m: Number of wait states in an external device access.
5.6.5 DTC and DMAC Activation by Interrupt
The DTC and DMAC can be activated by an interrupt. In this case, the following options are
available:
• Interrupt request to CPU
• Activation request to DTC
• Activation request to DMAC
• Selection of a number of the above
For details of interrupt requests that can be used to activate the DTC and DMAC, see table 5.2 and
section 9, Data Transfer Controller (DTC) and section 7, DMA Controller (DMAC).