Datasheet

Page xvi of xxx
9.4 Location of Register Information and DTC Vector Table ................................................. 485
9.5 Operation ........................................................................................................................... 489
9.5.1 Normal Mode........................................................................................................ 492
9.5.2 Repeat Mode......................................................................................................... 493
9.5.3 Block Transfer Mode ............................................................................................ 494
9.5.4 Chain Transfer ...................................................................................................... 495
9.5.5 Interrupt Sources................................................................................................... 496
9.5.6 Operation Timing.................................................................................................. 496
9.5.7 Number of DTC Execution States ........................................................................ 498
9.6 Procedures for Using DTC................................................................................................. 500
9.6.1 Activation by Interrupt.......................................................................................... 500
9.6.2 Activation by Software ......................................................................................... 500
9.7 Examples of Use of the DTC ............................................................................................. 501
9.7.1 Normal Mode........................................................................................................ 501
9.7.2 Chain Transfer ...................................................................................................... 502
9.7.3 Chain Transfer when Counter = 0......................................................................... 503
9.7.4 Software Activation .............................................................................................. 505
9.8 Usage Notes ....................................................................................................................... 506
9.8.1 Module Stop Function Setting .............................................................................. 506
9.8.2 On-Chip RAM ...................................................................................................... 506
9.8.3 DTCE Bit Setting.................................................................................................. 506
9.8.4 DMAC Transfer End Interrupt.............................................................................. 506
9.8.5 Chain Transfer ...................................................................................................... 506
Section 10 I/O Ports...........................................................................................507
10.1 Port 1.................................................................................................................................. 521
10.1.1 Port 1 Data Direction Register (P1DDR).............................................................. 521
10.1.2 Port 1 Data Register (P1DR)................................................................................. 522
10.1.3 Port 1 Register (PORT1)....................................................................................... 522
10.1.4 Port 1 Open Drain Control Register (P1ODR) ..................................................... 523
10.1.5 Pin Functions ........................................................................................................ 524
10.2 Port 2.................................................................................................................................. 547
10.2.1 Port 2 Data Direction Register (P2DDR).............................................................. 547
10.2.2 Port 2 Data Register (P2DR)................................................................................. 548
10.2.3 Port 2 Register (PORT2)....................................................................................... 548
10.2.4 Port 2 Open Drain Control Register (P2ODR) ..................................................... 549
10.2.5 Pin Functions ........................................................................................................ 550
10.3 Port 3.................................................................................................................................. 569
10.3.1 Port 3 Data Direction Register (P3DDR).............................................................. 569
10.3.2 Port 3 Data Register (P3DR)................................................................................. 570