Datasheet

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Section 8 EXDMA Controller (EXDMAC) ......................................................407
8.1 Features.............................................................................................................................. 407
8.2 Input/Output Pins...............................................................................................................409
8.3 Register Descriptions......................................................................................................... 410
8.3.1 EXDMA Source Address Register (EDSAR)....................................................... 410
8.3.2 EXDMA Destination Address Register (EDDAR)............................................... 411
8.3.3 EXDMA Transfer Count Register (EDTCR)........................................................ 411
8.3.4 EXDMA Mode Control Register (EDMDR) ........................................................ 413
8.3.5 EXDMA Address Control Register (EDACR) ..................................................... 418
8.4 Operation ........................................................................................................................... 422
8.4.1 Transfer Modes..................................................................................................... 422
8.4.2 Address Modes ..................................................................................................... 423
8.4.3 DMA Transfer Requests ....................................................................................... 427
8.4.4 Bus Modes ............................................................................................................ 428
8.4.5 Transfer Modes..................................................................................................... 430
8.4.6 Repeat Area Function ........................................................................................... 432
8.4.7 Registers during DMA Transfer Operation .......................................................... 435
8.4.8 Channel Priority Order.......................................................................................... 439
8.4.9 EXDMAC Bus Cycles (Dual Address Mode) ...................................................... 442
8.4.10 EXDMAC Bus Cycles (Single Address Mode) .................................................... 449
8.4.11 Examples of Operation Timing in Each Mode ..................................................... 454
8.4.12 Ending DMA Transfer.......................................................................................... 468
8.4.13 Relationship between EXDMAC and Other Bus Masters .................................... 469
8.5 Interrupt Sources................................................................................................................ 470
8.6 Usage Notes ....................................................................................................................... 472
Section 9 Data Transfer Controller (DTC) ........................................................475
9.1 Features.............................................................................................................................. 475
9.2 Register Descriptions......................................................................................................... 477
9.2.1 DTC Mode Register A (MRA) ............................................................................. 477
9.2.2 DTC Mode Register B (MRB).............................................................................. 479
9.2.3 DTC Source Address Register (SAR)................................................................... 480
9.2.4 DTC Destination Address Register (DAR)........................................................... 480
9.2.5 DTC Transfer Count Register A (CRA) ............................................................... 480
9.2.6 DTC Transfer Count Register B (CRB)................................................................ 480
9.2.7 DTC Enable Registers A to I (DTCERA to DTCERI) ......................................... 481
9.2.8 DTC Vector Register (DTVECR)......................................................................... 481
9.2.9 DTC Control Register (DTCCR) .......................................................................... 482
9.3 Activation Sources............................................................................................................. 483