Datasheet

Page 1380 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
DMTEND1A .......................................... 131
DMTEND1B .......................................... 131
DRAM interface ............................. 208, 222
DTC vector table .................................... 485
Dual address mode.................................. 423
E
Effective address extension ...................... 72
Ending DMA transfer ............................. 468
ERI0........................................................ 945
ERI1........................................................ 132
ERI2........................................................ 132
ERI3........................................................ 132
ERI4........................................................ 132
Exception handling................................... 95
Exception handling vector table ............... 96
EXDMA controller (EXDMAC) ............ 407
EXDMTEND2........................................ 131
EXDMTEND3........................................ 131
Extended register (EXR) .......................... 56
Extension of chip select (CS)
assertion period............................... 207, 220
External request mode ............................ 427
F
Flash memory ....................................... 1077
Framing error.......................................... 907
Full-scale error...................................... 1018
G
General call address................................ 969
General registers....................................... 55
I
I/O port states in each processing
state....................................................... 1337
I/O ports.................................................. 507
I
2
C bus format......................................... 971
I
2
C bus interface (IIC)............................. 955
Idle cycle................................................. 284
Idle mode ................................................ 353
IICI0................................................ 133, 134
IICI1................................................ 133, 134
Immediate ................................................. 76
Input capture function............................. 755
Input pull-up MOS.................................. 507
Instruction set............................................ 62
Interrupt control modes........................... 136
Interrupt exception handling................... 102
Interrupt exception handling vector
table ........................................................ 129
Interrupt mask bit...................................... 57
interrupt mask level .................................. 56
Interrupt priority register (IPR)............... 107
Interrupt sources ..................................... 400
Interval timer mode................................. 860
IrDA operation........................................ 940
IRQ0 ....................................................... 129
L
List of registers ..................................... 1163
Logic operations instructions.................... 67
M
Mark state ............................................... 948
MCU operating modes.............................. 83
Memory indirect ....................................... 77
Multi-channel operation.......................... 394
Multiply-accumulate register (MAC) ....... 58