Datasheet

R01UH0310EJ0500 Rev. 5.00 Page 1379 of 1384
Sep 25, 2012
Index
Numerics
16-Bit counter mode ............................... 844
16-Bit timer pulse unit (TPU)................. 701
8-Bit timer (TMR) .................................. 827
A
A/D conversion accuracy...................... 1018
A/D converter ......................................... 991
A/D converter activation......................... 783
Absolute accuracy................................. 1018
Absolute address....................................... 75
Acknowledge.............................. 7, 955, 972
Activation by external request ................ 347
Activation by software.................... 496, 500
Address mode ......................................... 423
Address space ........................................... 53
Addressing modes..................................... 74
Advanced mode ........................................ 51
Arithmetic operations ............................... 65
Asynchronous mode ............................... 900
Auto request mode.................................. 427
B
Basic timing............................................ 196
Bcc...................................................... 62, 70
Bit manipulation instructions.................... 68
Bit rate .................................................... 889
Block data transfer instructions ................ 72
Block transfer mode................ 367, 431, 494
Branch instructions................................... 70
Break....................................................... 948
Buffer operation...................................... 759
Burst mode...................................... 376, 429
Burst ROM interface............................... 281
Bus arbitration ........................................ 309
Bus controller (BSC)...............................149
Bus release ..............................................312
C
Cascaded connection............................... 844
Cascaded operation .................................763
Chain transfer.......................................... 495
Chain transfer when counter = 0 ............. 503
Clock pulse generator ...........................1131
Clock synchronous communication
mode .....................................................1067
Clocked synchronous mode .................... 918
CMI......................................................... 129
CMIA......................................................845
CMIA0....................................................131
CMIA1....................................................131
CMIB ...................................................... 845
CMIB0 .................................................... 131
CMIB1 .................................................... 131
Communications protocol ..................... 1103
Compare match count mode ...................844
Condition field ..........................................72
Condition-code register (CCR) .................57
CPU operating modes ............................... 49
Cycle steal mode..................................... 428
D
Data direction register.............................507
Data register............................................ 507
Data size and data alignment .................. 193
Data transfer controller (DTC)................ 475
Data transfer instructions ..........................64
DMA controller (DMAC) ....................... 315
DMTEND0A ..........................................131
DMTEND0B........................................... 131