Datasheet

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6.15.3 External Bus Release Function and CBR Refreshing/Auto Refreshing................ 312
6.15.4 BREQO Output Timing........................................................................................ 313
6.15.5 Notes on Usage of the Synchronous DRAM ........................................................ 313
Section 7 DMA Controller (DMAC)................................................................. 315
7.1 Features.............................................................................................................................. 315
7.2 Input/Output Pins...............................................................................................................317
7.3 Register Descriptions......................................................................................................... 318
7.3.1 Memory Address Registers (MARA and MARB)................................................ 320
7.3.2 I/O Address Registers (IOARA and IOARB)....................................................... 321
7.3.3 Execute Transfer Count Registers (ETCRA and ETCRB) ................................... 321
7.3.4 DMA Control Registers (DMACRA and DMACRB) .......................................... 323
7.3.5 DMA Band Control Registers H and L (DMABCRH and DMABCRL).............. 331
7.3.6 DMA Write Enable Register (DMAWER) ........................................................... 342
7.3.7 DMA Terminal Control Register (DMATCR) ..................................................... 344
7.4 Activation Sources............................................................................................................. 345
7.4.1 Activation by Internal Interrupt Request .............................................................. 346
7.4.2 Activation by Auto-Request ................................................................................. 347
7.5 Operation ........................................................................................................................... 347
7.5.1 Transfer Modes..................................................................................................... 347
7.5.2 Sequential Mode ................................................................................................... 350
7.5.3 Idle Mode.............................................................................................................. 353
7.5.4 Repeat Mode......................................................................................................... 356
7.5.5 Single Address Mode............................................................................................ 360
7.5.6 Normal Mode........................................................................................................ 363
7.5.7 Block Transfer Mode ............................................................................................ 367
7.5.8 Basic Bus Cycles .................................................................................................. 373
7.5.9 DMA Transfer (Dual Address Mode) Bus Cycles................................................ 374
7.5.10 DMA Transfer (Single Address Mode) Bus Cycles ............................................. 384
7.5.11 Write Data Buffer Function .................................................................................. 392
7.5.12 Multi-Channel Operation...................................................................................... 394
7.5.13 Relation between DMAC and External Bus Requests, Refresh Cycles, and
EXDMAC............................................................................................................. 396
7.5.14 DMAC and NMI Interrupts .................................................................................. 397
7.5.15 Forced Termination of DMAC Operation ............................................................ 398
7.5.16 Clearing Full Address Mode................................................................................. 399
7.6 Interrupt Sources................................................................................................................ 400
7.7 Usage Notes ....................................................................................................................... 401