Datasheet

Section 25 Electrical Characteristics
Page 1304 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
(3) Bus Timing
Table 25.45 Bus Timing (1)
Conditions: V
CC
= 4.5 V to 5.5 V, AV
CC
= 4.5 V to 5.5 V, V
ref
= 4.5 V to AV
CC
, V
SS
= AV
SS
= 0 V,
φ = 8 MHz to 33 MHz
Item Symbol Min. Max. Unit Test Conditions
Address delay time t
AD
⎯ 20 ns
Address setup time 1 t
AS1
0.5 × t
cyc
−13 ⎯ ns
Address setup time 2 t
AS2
1.0 × t
cyc
−13 ⎯ ns
Address setup time 3 t
AS3
1.5 × t
cyc
−13 ⎯ ns
Address setup time 4 t
AS4
2.0 × t
cyc
−13 ⎯ ns
Figures 25.58 to
25.68
Address hold time 1 t
AH1
0.5 × t
cyc
−8 ⎯ ns
Address hold time 2 t
AH2
1.0 × t
cyc
−8 ⎯ ns
Address hold time 3 t
AH3
1.5 × t
cyc
−8 ⎯ ns
CS delay time 1 t
CSD1
⎯ 15 ns
AS delay time t
ASD
⎯ 15 ns
RD delay time 1 t
RSD1
⎯ 15 ns
RD delay time 2 t
RSD2
⎯ 15 ns
Read data setup time 1 t
RDS1
15 ⎯ ns
Read data setup time 2 t
RDS2
15 ⎯ ns
Read data hold time 1 t
RDH1
0 ⎯ ns
Read data hold time 2 t
RDH2
0 ⎯ ns
Read data access time 2 t
AC2
⎯ 1.5 × t
cyc
− 25 ns
Read data access time 4 t
AC4
⎯ 2.5 × t
cyc
− 25 ns
Read data access time 5 t
AC5
⎯ 1.0 × t
cyc
− 25 ns
Counter address read data access time 1 t
AA1
⎯ 1.0 × t
cyc
− 25 ns
Counter address read data access time 2 t
AA2
⎯ 1.5 × t
cyc
− 25 ns
Counter address read data access time 3 t
AA3
⎯ 2.0 × t
cyc
− 25 ns
Counter address read data access time 4 t
AA4
⎯ 2.5 × t
cyc
− 25 ns
Counter address read data access time 5 t
AA5
⎯ 3.0 × t
cyc
− 25 ns
Counter address read data access time 6 t
AA6
⎯ 4.0 × t
cyc
− 25 ns
Multiplexed address delay time t
MAD
⎯ 20 ns
Multiplexed address setup time 1 t
MAS1
0.5 × t
cyc
− 15 ⎯ ns
Multiplexed address setup time 2 t
MAS2
1.5 × t
cyc
− 15 ⎯ ns
Multiplexed address hold time t
MAH
1.0 × t
cyc
− 15 ⎯ ns
AH delay time t
AHD
⎯ 15 ns