Datasheet

Section 4 Exception Handling
R01UH0310EJ0500 Rev. 5.00 Page 103 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
4.6 Trap Instruction Exception Handling
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The trap instruction exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.4 Status of CCR and EXR after Trap Instruction Exception Handling
CCR EXR
Interrupt Control Mode I UI I2 to I0 T
0 1 ⎯ ⎯ ⎯
2 1 ⎯ ⎯ 0
Legend:
1: Set to 1
0: Cleared to 0
⎯: Retains value prior to execution