Datasheet

Section 25 Electrical Characteristics
R01UH0310EJ0500 Rev. 5.00 Page 1289 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Item Symbol Min. Max. Unit
Test
Conditions
Counter address read data access
time 1
t
AA1
⎯ 1.0 × t
cyc
− 25 ns
Counter address read data access
time 2
t
AA2
⎯ 1.5 × t
cyc
− 25 ns
Counter address read data access
time 3
t
AA3
⎯ 2.0 × t
cyc
− 25 ns
Figures 25.58
to 25.73
Counter address read data access
time 4
t
AA4
⎯ 2.5 × t
cyc
− 25 ns
Counter address read data access
time 5
t
AA5
⎯ 3.0 × t
cyc
− 25 ns
Counter address read data access
time 6
t
AA6
⎯ 4.0 × t
cyc
− 25 ns
Multiplexed address delay time t
MAD
⎯ 20 ns
Multiplexed address setup time 1 t
MAS1
0.5 × t
cyc
− 15 ⎯ ns
Multiplexed address setup time 2 t
MAS2
1.5 × t
cyc
− 15 ⎯ ns
Multiplexed address hold time t
MAH
1.0 × t
cyc
− 15 ⎯ ns
AH delay time t
AHD
⎯ 15 ns