Datasheet

Page xiii of xxx
6.7.10 Byte Access Control ............................................................................................. 234
6.7.11 Burst Operation..................................................................................................... 236
6.7.12 Refresh Control..................................................................................................... 241
6.7.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface..... 247
6.8 Synchronous DRAM Interface........................................................................................... 250
6.8.1 Setting Continuous Synchronous DRAM Space................................................... 250
6.8.2 Address Multiplexing ........................................................................................... 251
6.8.3 Data Bus ............................................................................................................... 252
6.8.4 Pins Used for Synchronous DRAM Interface....................................................... 252
6.8.5 Synchronous DRAM Clock.................................................................................. 254
6.8.6 Basic Timing......................................................................................................... 254
6.8.7 CAS Latency Control............................................................................................ 256
6.8.8 Row Address Output State Control....................................................................... 258
6.8.9 Precharge State Count........................................................................................... 259
6.8.10 Bus Cycle Control in Write Cycle ........................................................................ 261
6.8.11 Byte Access Control ............................................................................................. 262
6.8.12 Burst Operation..................................................................................................... 265
6.8.13 Refresh Control..................................................................................................... 269
6.8.14 Mode Register Setting of Synchronous DRAM.................................................... 275
6.8.15 DMAC and EXDMAC Single Address Transfer Mode and Synchronous
DRAM Interface ................................................................................................... 276
6.9 Burst ROM Interface.......................................................................................................... 281
6.9.1 Basic Timing......................................................................................................... 281
6.9.2 Wait Control ......................................................................................................... 283
6.9.3 Write Access......................................................................................................... 283
6.10 Idle Cycle........................................................................................................................... 284
6.10.1 Operation .............................................................................................................. 284
6.10.2 Pin States in Idle Cycle......................................................................................... 303
6.11 Write Data Buffer Function ............................................................................................... 304
6.12 Bus Release........................................................................................................................ 305
6.12.1 Operation .............................................................................................................. 305
6.12.2 Pin States in External Bus Released State ............................................................ 306
6.12.3 Transition Timing ................................................................................................. 307
6.13 Bus Arbitration .................................................................................................................. 309
6.13.1 Operation .............................................................................................................. 309
6.13.2 Bus Transfer Timing............................................................................................. 310
6.14 Bus Controller Operation in Reset ..................................................................................... 311
6.15 Usage Notes ....................................................................................................................... 312
6.15.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............. 312
6.15.2 External Bus Release Function and Software Standby ......................................... 312