Datasheet

Section 25 Electrical Characteristics
Page 1244 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Item Symbol Min. Max. Unit Test Conditions
Master 4 256 t
cyc
SSU* Clock cycle
Slave
t
SUcyc
4 256
Figures 25.48 to
25.51
Master 48 ⎯ Clock high pulse
width
Slave
t
HI
48 ⎯
ns
Master 48 ⎯ Clock low pulse
width
Slave
t
LO
48 ⎯
ns
Clock rising time t
RISE
⎯ 12 ns
Clock falling time t
FALL
⎯ 12 ns
Master 25 ⎯ Data input setup
time
Slave
t
SU
30 ⎯
ns
Master 10 ⎯ Data input hold
time
Slave
t
H
10 ⎯
ns
Master 2.5 ⎯ SCS setup time
Slave
t
LEAD
2.5 ⎯
t
cyc
Master 2.5 ⎯ SCS hold time
Slave
t
LAG
2.5 ⎯
t
cyc
Master ⎯ 40 Data output delay
time
Slave
t
OD
⎯ 40
ns
Master −5 ⎯ Data output hold
time
Slave
t
OH
0 ⎯
ns
Master 2.5 ⎯ Continuous
transmit delay time
Slave
t
TD
2.5 ⎯
t
cyc
Slave access time t
SA
⎯ 1 t
cyc
Slave out release time t
REL
⎯ 1 t
cyc
Figures 25.50
and 25.51
Note * SSU: Synchronous serial communication unit