Datasheet

Section 4 Exception Handling
R01UH0310EJ0500 Rev. 5.00 Page 95 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Section 4 Exception Handling
4.1 Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, illegal
instruction, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or
more exceptions occur simultaneously, they are accepted and processed in order of priority.
Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt
control mode. For details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1 Exception Types and Priority
Priority Exception Type Start of Exception Handling
High Reset Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU
enters the reset state when the RES pin is low.
Illegal instruction Starts when execution of an illegal instruction code is
detected.
Trace*
1
Starts when execution of the currently executed instruction
or exception handling ends, if the trace (T) bit in the EXR is
set to 1.
Direct transition*
2
Starts when the direct transition occurs by execution of the
SLEEP instruction.
Interrupt Starts when execution of the current instruction or
exception handling ends, if an interrupt request has been
issued. *
3
Low Trap instruction*
4
Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Not available in this LSI.
3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
4. Trap instruction exception handling requests are accepted at all times in program
execution state.