Datasheet

Section 24 List of Registers
Page 1178 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Register Name Abbreviation
Number
of Bits Address Module
Data
Width
Access
States
Timer mode register_0 TMDR_0 8 H'FFD1 TPU_0 16 2
Timer I/O control register H_0 TIORH_0 8 H'FFD2 TPU_0 16 2
Timer I/O control register L_0 TIORL_0 8 H'FFD3 TPU_0 16 2
Timer interrupt enable register_0 TIER_0 8 H'FFD4 TPU_0 16 2
Timer status register_0 TSR_0 8 H'FFD5 TPU_0 16 2
Timer counter_0 TCNT_0 16 H'FFD6 TPU_0 16 2
Timer general register A_0 TGRA_0 16 H'FFD8 TPU_0 16 2
Timer general register B_0 TGRB_0 16 H'FFDA TPU_0 16 2
Timer general register C_0 TGRC_0 16 H'FFDC TPU_0 16 2
Timer general register D_0 TGRD_0 16 H'FFDE TPU_0 16 2
Timer control register_1 TCR_1 8 H'FFE0 TPU_1 16 2
Timer mode register_1 TMDR_1 8 H'FFE1 TPU_1 16 2
Timer I/O control register_1 TIOR_1 8 H'FFE2 TPU_1 16 2
Timer interrupt enable register_1 TIER_1 8 H'FFE4 TPU_1 16 2
Timer status register_1 TSR_1 8 H'FFE5 TPU_1 16 2
Timer counter_1 TCNT_1 16 H'FFE6 TPU_1 16 2
Timer general register A_1 TGRA_1 16 H'FFE8 TPU_1 16 2
Timer general register B_1 TGRB_1 16 H'FFEA TPU_1 16 2
Timer control register_2 TCR_2 8 H'FFF0 TPU_2 16 2
Timer mode register_2 TMDR_2 8 H'FFF1 TPU_2 16 2
Timer I/O control register_2 TIOR_2 8 H'FFF2 TPU_2 16 2
Timer interrupt enable register_2 TIER_2 8 H'FFF4 TPU_2 16 2
Timer status register_2 TSR_2 8 H'FFF5 TPU_2 16 2
Timer counter_2 TCNT_2 16 H'FFF6 TPU_2 16 2
Timer general register A_2 TGRA_2 16 H'FFF8 TPU_2 16 2
Timer general register B_2 TGRB_2 16 H'FFFA TPU_2 16 2
Notes: 1. If the pulse output group 2 and pulse output group 3 output triggers are the same
according to the PCR setting, the NDRH address will be H'FF4C, and if different, the
address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different,
the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
2. For writing, see section 14.6.1, Notes on Register Access.
3. Not supported by the H8S/2424 Group.