Datasheet

Page xii of xxx
6.3.6 Area 0 Burst ROM Interface Control Register (BROMCRH)
Area 1 Burst ROM Interface Control Register (BROMCRL) .............................. 167
6.3.7 Bus Control Register (BCR) ................................................................................. 168
6.3.8 Address/Data Multiplexed I/O Control Register (MPXCR) ................................. 170
6.3.9 DRAM Control Register (DRAMCR) .................................................................. 171
6.3.10 DRAM Access Control Register (DRACCR)....................................................... 179
6.3.11 Refresh Control Register (REFCR) ...................................................................... 182
6.3.12 Refresh Timer Counter (RTCNT)......................................................................... 185
6.3.13 Refresh Time Constant Register (RTCOR) .......................................................... 185
6.4 Bus Control........................................................................................................................ 186
6.4.1 Area Division........................................................................................................ 186
6.4.2 Bus Specifications ................................................................................................ 187
6.4.3 Memory Interfaces................................................................................................ 189
6.4.4 Chip Select Signals ............................................................................................... 191
6.5 Basic Bus Interface ............................................................................................................ 193
6.5.1 Data Size and Data Alignment.............................................................................. 193
6.5.2 Valid Strobes ........................................................................................................ 195
6.5.3 Basic Timing......................................................................................................... 196
6.5.4 Wait Control ......................................................................................................... 204
6.5.5 Read Strobe (RD) Timing..................................................................................... 205
6.5.6 Extension of Chip Select (CS) Assertion Period................................................... 207
6.6 Address/Data Multiplexed I/O Interface............................................................................ 208
6.6.1 Setting Address/Data Multiplexed I/O Space ....................................................... 208
6.6.2 Address/Data Multiplexing................................................................................... 208
6.6.3 Data Bus ............................................................................................................... 209
6.6.4 Address Hold Signal ............................................................................................. 209
6.6.5 Basic Timing......................................................................................................... 209
6.6.6 Wait Control ......................................................................................................... 218
6.6.7 Read Strobe (RD) Timing..................................................................................... 219
6.6.8 Extension of Chip Select (CS) Assertion Period in Data Cycle............................ 220
6.7 DRAM Interface ................................................................................................................ 222
6.7.1 Setting DRAM Space............................................................................................ 222
6.7.2 Address Multiplexing ........................................................................................... 222
6.7.3 Data Bus ............................................................................................................... 223
6.7.4 Pins Used for DRAM Interface............................................................................. 224
6.7.5 Basic Timing......................................................................................................... 225
6.7.6 Column Address Output Cycle Control................................................................ 227
6.7.7 Row Address Output State Control....................................................................... 228
6.7.8 Precharge State Control ........................................................................................ 230
6.7.9 Wait Control ......................................................................................................... 231