Datasheet

Section 23 Power-Down Modes
R01UH0310EJ0500 Rev. 5.00 Page 1161 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
23.5 Usage Notes
23.5.1 I/O Port Status
In software standby mode, I/O port states are retained. Therefore, there is no reduction in current
dissipation for the output current when a high-level signal is output.
23.5.2 Current Dissipation during Oscillation Stabilization Standby Period
Current dissipation increases during the oscillation stabilization standby period.
23.5.3 EXDMAC, DMAC, and DTC Module Stop
Depending on the operating status of the EXDMAC, DMAC, or DTC, the MSTP14 to MSTP13
and may not be set to 1. Setting of the EXDMAC, DMAC, or DTC module stop state should be
carried out only when the respective module is not activated.
For details, see section 8, EXDMA Controller (EXDMAC), section 7, DMA Controller (DMAC),
and section 9, Data Transfer Controller (DTC).
Note: The EXDMAC is not supported by the H8S/2424 group.
23.5.4 On-Chip Peripheral Module Interrupts
Relevant interrupt operations cannot be performed in the module stop state. Consequently, if the
module stop state is entered when an interrupt has been requested, it will not be possible to clear
the CPU interrupt source or the DMAC or DTC activation source.
Interrupts should therefore be disabled before entering the module stop state.
Note: The EXDMAC is not supported by the H8S/2424 group.
23.5.5 Writing to MSTPCR, EXMSTPCR, and RMMSTPCR
MSTPCR, EXMSTPCR, and RMMSTPCR should only be written to by the CPU.