Datasheet

Section 23 Power-Down Modes
R01UH0310EJ0500 Rev. 5.00 Page 1147 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
23.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
MSTPCR performs module stop state control. Setting a bit to 1, the corresponding module enters
the module stop state, while clearing the bit to 0 clears the module stop state.
• MSTPCRH
Bit Bit Name Initial Value R/W Module
15 ACSE 0 R/W All Module Clocks Stop Mode Enable
Enables or disables all module clocks stop mode,
in which, when the CPU executes a SLEEP
instruction after the module stop state has been
set for all the on-chip peripheral functions
controlled by MSTPCR and EXMSTPCR or the
on-chip peripheral functions except the TMR.
0: All module clocks stop mode disabled
1: All module clocks stop mode enabled
14 MSTP14 0 R/W EXDMA controller (EXDMAC)*
13 MSTP13 0 R/W DMA controller (DMAC)
12 MSTP12 0 R/W Data transfer controller (DTC)
11 MSTP11 1 R/W 16-bit timer pulse unit 0 (TPU_0)
10 MSTP10 1 R/W Programmable pulse generator (PPG)
9 MSTP9 1 R/W 16-bit timer pulse unit 1 (TPU_1)
8 MSTP8 1 R/W D/A converter (channels 2 and 3)
Note: * Not supported by the H8S/2424 group.