Datasheet

Section 23 Power-Down Modes
R01UH0310EJ0500 Rev. 5.00 Page 1141 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Section 23 Power-Down Modes
In addition to the normal program execution state, this LSI has power-down modes in which
operation of the CPU and oscillator is halted and power consumption is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and
so on.
This LSI’s operating modes are high-speed mode and six power down modes:
• Clock division mode
• Sleep mode
• Module stop function
• All module clocks stop mode
• Software standby mode
• Hardware standby mode
Sleep mode is a CPU state, clock division mode is an on-chip peripheral function (including bus
masters and the CPU) state, and module stop function is an on-chip peripheral function (including
bus masters other than the CPU) state. A combination of these modes can be set.
After a reset, this LSI is in high-speed mode.
Table 23.1 shows the internal states of this LSI in each mode. Figure 23.1 shows the mode
transition diagram.