Datasheet

Section 3 MCU Operating Modes
R01UH0310EJ0500 Rev. 5.00 Page 87 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
3.3.4 Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in the on-chip ROM connected to the first half of area 0 is executed.
Ports A to C function as input ports immediately after a reset, but can be set to function as an
address bus depending on each port register setting. Port D functions as a data bus and parts of
ports F to H function as bus control signals. For details on function switching of ports A to C, see
section 10, I/O Ports.
The initial bus mode immediately after a reset is 8 bits, with 8-bit access to all areas. However, if
16-bit access is designated for any one of the areas by the bus controller, the bus mode switches to
16 bits and port E functions as a data bus.
In the flash memory version, user program mode is entered by clearing the CBIDB bit to 0 and
setting the FMCMDEN bit to 1 in FLMCR1.
3.3.5 Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
and the LSI starts up in single-chip mode. External address spaces cannot be used in single-chip
mode.
The initial mode immediately after a reset is single-chip mode, with all I/O ports available for use
as input/output ports. However, setting the EXPE bit in SYSCR to 1 switches the mode to an
externally expanded mode in which the external address spaces are enabled. When an externally
expanded mode is selected, all areas are initially designated as a 16-bit access space. The functions
of pins in ports A to H are the same as those in an externally expanded mode with on-chip ROM
enabled.
In the flash memory version, user program mode is entered by clearing the CBIDB bit to 0 and
setting the FMCMDEN bit to 1 in FLMCR1.