Datasheet

Section 3 MCU Operating Modes
Page 84 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
3.2 Register Descriptions
The following registers are related to operating mode setting.
• Mode control register (MDCR)
• System control register (SYSCR)
3.2.1 Mode Control Register (MDCR)
MDCR monitors the current operating mode of this LSI.
Bit Bit Name Initial Value R/W Descriptions
7 to 3 ⎯ All 0 ⎯ Reserved
These bits are always read as 0 and cannot be
modified.
2
1
0
MDS2
MDS1
MDS0
⎯*
⎯*
⎯*
R
R
R
Mode Select 2 to 0
These bits indicate the input levels at mode pins
MD2 to MD0 (the current operating mode). Bits
MDS2 to MDS0 correspond to pins MD2 to MD0,
respectively. These bits are read-only bits and so
they cannot be modified. The input levels of the
MD2 to MD0 pins are latched into these bits when
MDCR is read. These latches are canceled by a
reset.
Note: * Determined by the settings of pins MD2 to MD0.
3.2.2 System Control Register (SYSCR)
SYSCR selects saturation operation for the MAC instruction, controls CPU access to the flash
memory control registers, sets the external bus mode, and enables or disables on-chip RAM.
Bit Bit Name Initial Value R/W Descriptions
7, 6 ⎯ All 1 R/W Reserved
The initial value should not be modified.
5 MACS 0 R/W MAC Saturation Operation Control
Selects either saturation operation or non-saturation
operation for the MAC instruction.
0: MAC instruction performs non-saturation operation
1: MAC instruction performs saturation operation