Datasheet

Section 21 Flash Memory
Page 1096 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
21.6 Full Status Check
When an error occurs, the FMERSF or FMPRSF bit in FLMSTR becomes 1 to indicate
occurrence of the error. Read these status bits (full status check) to check the operation results.
Table 21.7 shows the errors and FLMSTR status and figure 21.6 shows a flowchart of full status
check processing and corrective actions for each error.
Table 21.7 Errors and Register Status
State of FLMSTR
(Status Register)
FMERSF Bit
(SR5)
FMPRSF Bit
(SR4) Error Error Conditions
1 1 Command
sequence error
• When a command is not issued correctly
• When an invalid value (a value other than
H'D0xx or H'FFxx) is written in the second
bus cycle of a block erase command*
1 0 Erase error
• When a block erase command is issued but
the block is not erased correctly
• When a block blank check command is
issued and the checked block is not blank
0 1 Programming
error
• When a program command is issued but
automatic writing is not done correctly
Note: * When H'FFxx is written in the second bus cycle of this command, the flash memory
enters the read array mode and the command code written in the first bus cycle is
ignored.