Datasheet

Section 21 Flash Memory
R01UH0310EJ0500 Rev. 5.00 Page 1089 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
21.4.4 Program
This command writes data to the flash memory in 2-word units.
Write H'41xx in the first bus cycle and write data to the target address in the second and third bus
cycles; the flash memory starts automatic writing (programming and verifying data). The address
value specified in the first bus cycle should be the same even address as that specified in the
second bus cycle.
Completion of automatic writing can be checked through the FMRDY bit in FLMSTR. The
FMRDY bit is 0 (busy) during automatic writing and becomes 1 (ready) when writing is
completed.
After automatic writing is completed, the result can be checked through the FMPRSF bit in
FMRSTR (refer to section 21.6, Full Status Check).
Once an address is programmed, no additional data can be written to the address. Figure 21.3
shows a flowchart of the program command processing.
In the EW0 mode, the read status register mode is entered as soon as automatic writing starts, and
the status register can be read. The SR7 bit in the status register becomes 0 when automatic
writing starts and returns to 1 when writing is completed. In this case, the flash memory stays in
the read status register mode until a read array command is issued. After automatic writing is
completed, the result of writing can be checked by reading the status register.