Datasheet

Section 21 Flash Memory
R01UH0310EJ0500 Rev. 5.00 Page 1081 of 1384
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
21.2.1 Flash Memory Control Register 1 (FLMCR1)
Bit Bit Name
Initial
Value R/W Description
7 ⎯ 0 ⎯ Reserved
The initial value should not be changed.
6 CBIDB 1 R/W CPU Programming Mode Select
Setting this bit to 0 (CPU programming mode) enables
command acceptance.
0: CPU programming mode enabled
1: CPU programming mode disabled
5 ⎯ 0 ⎯ Reserved
The initial value should not be changed.
4 ⎯ 0 ⎯ Reserved
The initial value should not be changed.
3 ⎯ 0 ⎯ Reserved
The initial value should not be changed.
2 ⎯ 1 ⎯ Reserved
The initial value should not be changed.
1 ⎯ 0 ⎯ Reserved
The initial value should not be changed.
0 FMCMDEN 0 R/W Flash Memory Software Command Enable
Setting this bit to 1 (CPU programming mode) enables
command acceptance.
0: Flash memory software commands disabled
1: Flash memory software commands enabled
To set this bit to 1, be sure to write 0 and then write 1 in a
row.