Datasheet

Section 19 Synchronous Serial Communication Unit (SSU)
Page 1074 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
19.5 Interrupt Requests
The SSU interrupt requests are an overrun error, a conflict error, a receive data register full,
transmit data register empty, and a transmit end interrupts.
Since both an overrun error and a conflict error interrupts are allocated to the SSERI vector
address, and both a transmit data register empty and a transmit end interrupts are allocated to the
SSTXI vector address, the interrupt source should be decided by their flags. Table 19.7 lists the
interrupt sources.
When an interrupt condition shown in table 19.7 is satisfied, an interrupt is requested. Clear the
interrupt source by CPU or DMAC data transfer.
Table 19.7 Interrupt Sources
Channel Abbreviation Interrupt Source Symbol Interrupt Condition
DMAC
Activation
0 SSERI0 Overrun error OEI0 (RIE = 1) • (ORER = 1) ⎯
Conflict error CEI0 (CEIE = 1) • (CE = 1) ⎯
SSRXI0 Receive data register full RXI0 (RIE = 1) • (RDRF = 1) ⎯
SSTXI0 Transmit data register empty TXI0 (TIE = 1) • (TDRE = 1) ⎯
Transmit end TEI0 (TEIE = 1) • (TEND = 1) ⎯
19.6 Usage Note
19.6.1 Module Stop Function Setting
SSU operation can be disabled or enabled using the module stop control register. The initial
setting is for the SSU to be halted. Register access is enabled by clearing the module stop state.
For details, see section 23, Power-Down Modes.