Datasheet

Section 19 Synchronous Serial Communication Unit (SSU)
Page 1062 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit
0
to to to to
to to to to
Bit
0
Bit
7
Bit
7
Bit
0
Bit
7
Bit
0
Bit
7
Bit
0
Bit
7
Bit
0
Bit
7
Bit
0
Bit
7
Bit
0
Bit
7
LSI operation
User operation
SSI
(LSB first)
SSI
(MSB first)
SCS
SSCK
RDRF
SSRDR0
SSRDR3
SSRDR1
SSRDR2
SSRDR2
SSRDR1
SSRDR3
SSRDR0
1 frame
Dummy-read SSRDR0, SSRDR1,
SSRDR2 and SSRDR3
RXI interrupt
generated
Figure 19.7 Example of Reception Operation (SSU Mode)
When 32-Bit Data Length is Selected (SSRDR0, SSRDR1, SSRDR2 and SSRDR3 are Valid)
with CPOS = 0 and CPHS = 0 (4)