Datasheet

Section 19 Synchronous Serial Communication Unit (SSU)
Page 1046 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
Bit Bit Name
Initial
Value R/W Description
2 TDRE 1 R/W Transmit Data Empty
Indicates whether or not SSTDR contains transmit data.
[Setting conditions]
• When the TE bit in SSER is 0
• When data is transferred from SSTDR to SSTRSR
and SSTDR is ready to be written to.
[Clearing conditions]
• When writing 0 after reading TDRE = 1
• When writing data to SSTDR with TE = 1
1 RDRF 0 R/W Receive Data Register Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
• When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
[Clearing conditions]
• When writing 0 after reading RDRF = 1
• When reading receive data from SSRDR
0 CE 0 R/W Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master device).
If the SCS pin level changes to 1 with SSUMS = 0
(SSU mode) and MSS = 0 (slave device), an
incomplete error occurs because it is determined that a
master device has terminated the transfer. Data
reception does not continue while the CE bit is set to 1.
Serial transmission also does not continue. Reset the
SSU internal sequencer by setting the SRES bit in
SSCRL to 1 before resuming transfer after incomplete
error.
[Setting condition]
• When a low level is input to the SCS pin in master
device (the MSS bit in SSCRH is set to 1)
• When the SCS pin is changed to 1 during transfer in
slave device (the MSS bit in SSCRH is cleared to 0)
[Clearing condition]
• When writing 0 after reading CE = 1