Datasheet

Section 19 Synchronous Serial Communication Unit (SSU)
Page 1042 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
19.3.2 SS Control Register L (SSCRL)
SSCRL selects operating mode, software reset, and transmit/receive data length.
Bit Bit Name
Initial
Value R/W Description
7 ⎯ 0 R/W Reserved
This bit is always read as 0. The write value should
always be 0.
6 SSUMS 0 R/W Selects transfer mode from SSU mode and clock
synchronous mode.
0: SSU mode
1: Clock synchronous mode
5 SRES 0 R/W Software Reset
Setting this bit to 1 forcibly resets the SSU internal
sequencer. After that, this bit is automatically cleared.
The ORER, TEND, TDRE, RDRF, and CE bits in SSSR
and the TE and RE bits in SSER are also initialized.
Values of other bits for SSU registers are held.
To stop transfer, set this bit to 1 to reset the SSU
internal sequencer.
4 to 2 ⎯ All 0 R/W Reserved
These bits are always read as 0. The write value should
always be 0.
1
0
DATS1
DATS0
0
0
R/W
R/W
Transmit/Receive Data Length Select
Select serial data length.
00: 8 bits
01: 16 bits
10: 32 bits
11: 24 bits