Datasheet

Section 16 I2C Bus Interface 2 (IIC2)
Page 986 of 1384 R01UH0310EJ0500 Rev. 5.00
Sep 25, 2012
H8S/2426, H8S/2426R, H8S/2424 Group
16.5 Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK detection, STOP recognition, and arbitration lost. Table 16.3 shows the contents of each
interrupt request.
Table 16.3 Interrupt Requests
Interrupt Request Abbreviation Interrupt Condition
Transmit Data Empty TXI (TDRE=1)
•
(TIE=1)
Transmit End TEI (TEND=1)
•
(TEIE=1)
Receive Data Full RXI (RDRF=1)
•
(RIE=1)
STOP Recognition STPI (STOP=1)
•
(STIE=1)
NACK Detection
Arbitration Lost
NAKI {(NACKF=1)+(AL=1)}
•
(NAKIE=1)
Interrupt exception handling is performed when the interrupt conditions listed in table 16.3 are set
to 1 and the CPU is ready to accept interrupts. During exception handling, the interrupt sources
should be cleared. Note, however, that TDRE and TEND are automatically cleared by writing
transmit data to ICDRT, and RDRF is automatically cleared by reading data from ICDRR. In
particular, if TDRE is set at the same time transmit data is written to ICDRT, and then TDRE is
cleared again, an extra byte of data may be transmitted.